The present invention relates generally to digital delay lines, and more specifically to an integrated digital delay line scheme with programmable delay capability.
Digital delay lines have a variety of applications, e.g., in pulse-shapers, in clock de-skewing circuits, as well as in serial data re-synchronization circuits. The application of interest here is serial data re-synchronization and clock recovery in hard disk drive read channel circuitry. In this application, the delay line is used as an "anticipator" delay in a clock recovery phase-locked loop (PLL). This allows the PLL to "look-ahead" within the incoming data stream and anticipate the presence or absence of data pulses, enabling the loop to remain locked to quasi-random data patterns without interpreting "missing" data pulses as drops in input frequency. The delay line can also serve the function of aligning the data re-synchronization (bit capture) window in this type of application.
FIG. 1 shows a conventional scheme employed for this purpose as shown in National Semiconductor Mass Storage Handbook, 1989, pp. 2-38 and 2-39, incorporated herein by reference. Variation of the delay line magnitude, T.sub.d, produces a proportional shift in the position (centering) of the data window. This is useful for de-skewing purposes or channel margin testing.
FIG. 2 shows an alternate scheme where the delay line has two outputs: a nominal output used for PLL phase comparisons, and a second, variable output used by the bit capture circuitry (data latch) for data re-synchronization as described in U.S. Pat. No. 5,097,489 to Tucci, assigned to the assignee of the present invention and incorporated herein by reference. Variation of the delay at the variable output moves the data re-synchronization window without disturbing the phase equilibrium of the PLL.
The circuit techniques used to achieve controlled delay vary significantly. The delay line of FIG. 1 employs a starved ring oscillator and a 5-bit programmable counter. The ring oscillator operates over a 3:1 frequency range while the counter extends the effective delay line operation to 100:1 as described in "A 33 Mb/s Data Synchronizing Phase-Locked Loop Circuit," ISSCC Digest of Technical Papers, vol. 31, February 1988, pp. 12-13; incorporated herein by reference. The half-cell delay line of FIG. 2 is comprised of a multiplicity of differential delay stages and an M-wide multiplexer. The M-inputs of the multiplexer are connected to M sequential tap points within the delay line; the output of the multiplexer is the variable delay output whose timing is simply a function of the selected delay line tap. It should be noted that, to generate a delayed signal, only the two outputs of any particular delay stage are used.
Jitter is also an important consideration in delay line construction, since it is undesirable to add any random or uncontrolled time modulation to the digital pulses being passed through the delay line. This would be particularly true if starved delay stage elements were being used and the delay line were to be closed on itself for use as a ring oscillator. In this case the jitter of each stage would accumulate as the pulse circulated around within the ring, exacerbating the jitter problem.
Of the three types of conventional digital gates which can be used as starved delay elements, the type which exhibits the least per-stage jitter is a simple, fast-skewing inverter, such as that described in "High Speed Clock Recovery in VLSI Using Hybrid Analog/Digital Techniques," by Beomsup Kim, Memorandum No. UCB/ERL M90/50, 6 Jun. 1990, Elec. Research Lab., UC Cal., Berkeley, Calif., page 81, incorporated herein by reference. Unfortunately, a unipolar pulse traversing an inverter-based delay line produces edges of opposite sense (polarity) at each node. In order to prevent odd tap number inversion, some schemes use every other inverter output for each tap point (FIG. 3). However, this reduces the resolution of the delay taps by doubling the time displacement between them and increases the number of delay elements needed. Other schemes use differential delay elements where either signal sense is available, although differential delay elements tend to be slower than simple inverters, again sacrificing resolution.
For these reasons, a digital delay line is desired with a lower number of delay elements in comparison with the prior art, with a lower number of tap connections with the multiplexers in the system and which offers a low jitter system alternative.